? semiconductor components industries, llc, 2011 august, 2011 ? rev. 1 1 publication order number: ncp391/d ncp391 positive overvoltage protection controller with internal low r on nmos fet the ncp391 is able to disconnect the systems from its output pin when wrong input operating conditions are detected. the system is positive overvoltage protected up to +28 v. this device uses an internal nmos and therefore, no external device is necessary, reducing the system cost and the pcb area of the application board. the ncp391 is able to instantaneously disconnect the output from the input, due to integrated low r on power nmos, if the input voltage exceeds the overvoltage threshold (ovlo) or falls below the undervoltage threshold (uvlo). at powerup ( en pin = low level), the v out turns on t on time after the v in exceeds the undervoltage threshold. the ncp391 provides a negative going flag ( flag ) output, which alerts the system that a fault has occurred. in addition, the device has esd ? protected input (15 kv air) when bypassed with a 1.0 f or larger capacitor. features ? overvoltage protection up to 28 v ? on ? chip low r ds(on) nmos transistor ? internal charge pump ? overvoltage lockout (ovlo) ? undervoltage lockout (uvlo) ? soft ? start ? alert flag output ? shutdown en input ? compliance to iec61000 ? 4 ? 2 (level 4) 8.0 kv (contact) 15 kv (air) ? esd ratings: machine model = b human body model = 2 ? wlcsp6 1.31x1.04 mm package ? this is a pb ? free device applications ? cell phones ? camera phones ? digital still cameras ? personal digital applications ? mp3 players wlcsp6 fc suffix case 499bp pin connections http://onsemi.com marking diagram (top view) flag 4 gnd 5 out 3 in 1 en 6 q ordering information see detailed ordering, marking and shipping information in the package dimensions section on page 11 of this data sheet. in 2 xxxx ayww xxxx = specific device code a = assembly location y = year ww = work week = pb ? free package (top view) flag b3 gnd b2 out a3 in a1 en b1 in a2 or
ncp391 http://onsemi.com 2 figure 1. t ypical application circuit in 1 out 3 gnd 6 5 in 2 4 ncp391 0 1 f 10 k wall adapter ? ac/dc ? usb battery 0 cc/cv charger or system v cc enable/ microprocessor en flag p b+ figure 2. functional block diagram input uvlo ovlo tsd gate driver flag en en block v ref charge pump control logic and timer gnd 1 2 6 5 4 3
ncp391 http://onsemi.com 3 pin function description pin no. symbol function description 1, 2 or a1, a2 in input input voltage pins. these pins are connected to the wall adapoter (ac ? dc, vbus ..). a 1 f low esr ceramic capacitor, or larger, must be connected between these pins and gnd, as close as possible to the dut. the two in pins must be connected together to power supply. (see pcb recom- mendation for the pin7). 3 or a3 out output output voltage pins. this pin follows in pins when ?no fault? is detected. 4 or b3 flag output fault indication pin. this pin allows an external system to detect a fault on the in pins. the flag pin goes low when input voltage exceeds ovlo threshold or drops below uvlo threshold or when tsd is exceeded. since the flag pin is open drain functionality, an external pull ? up resistor to v cc must be added. (minimum 10 k ). 5 or b2 gnd power ground 6 or b1 en input enable pin. the device enters in shutdown mode when this pin is tied to a high level. in this case the output is disconnected from the input. to allow normal functionality, the en pin shall be connected to gnd to a pull down or to a i/o pin. this pin does not have an impact on the fault detection. maximum ratings rating symbol value unit minimum v oltage (in to gnd) vmin in ? 0.3 v minimum v oltage (all others to gnd) vmin ? 0.3 v maximum voltage (in to gnd) vmax in 30 v maximum voltage (all others to gnd) vmax 7.0 v maximum current (uvlo ncp391 http://onsemi.com 4 electrical characteristics (min/max limits values ( ? 40 c < t a < +85 c) and v in = +5.0 v. typical values are t a = +25 c, unless otherwise noted.) characteristic symbol conditions min typ max unit input voltage range v in ? 1.2 ? 28 v undervoltage lockout threshold (note 4) ncp391fcal uvlo v in falls below uvlo threshold from 5 v to 2.7 v 2.8 2.95 3.1 v undervoltage lockout hysteresis uvlo hyst v in rises above uvlo + uvlo hyst 30 60 90 mv overvoltage lockout threshold (note 4) ncp391fcal ovlo v in rises above ovlo threshold 7.16 7.4 7.65 v overvoltage lockout hysteresis ncp391fcal ovlo hyst v in falls below ovlo + ovlo hyst 50 100 150 mv v in versus v out resistance r ds(on) v in = 5.0 v, en = gnd, load connected to v out ? 120 200 m supply quiescent current idd no load. en = 5.0 v ? 70 150 a no load. en = gnd ? 90 170 a uvlo supply current idd uvlo v in = 2.7 v ? 60 ? a mosfet leakage i vdss v in = 28 v ? 10 500 na flag output low voltage vol flag 1.2 v < v in < uvlo sink 50 a on/flag pin ? 20 400 mv v in > ovlo sink 1.0 ma on flag pin ? ? 400 mv flag leakage current flag leak flag level = 5.0 v ? 1.0 ? na en voltage high vih ? 1.2 ? ? v en voltage low vol ? ? ? 0.4 v en leakage current en leak en = 5.0 v or gnd ? 1.0 ? na thermal shutdown t emperature t sd ? ? 150 ? c thermal shutdown hysteresis t sdhyst ? ? 15 ? c timings startup delay ton from v in > uvlo to v out = 0.3 v (see figures 3 & 7) 6.0 10 14 ms flag going up delay tstart from v out = 0.3 v to flag = 1.2 v (see figures 3 & 9) 6.0 10 14 ms output turn off time toff from v in > ovlo to v out < = 0.3 v (see figures 4 & 8) v in increasing from 5.0 v to 8.0 v at 3.0 v/ s rload connected on v out ? 1.5 5.0 s alert delay tstop from v in > ovlo to flag < = 0.4 v (see figures 4 & 10) v in increasing from 5.0 v to 8.0 v at 3.0 v/ s rload connected on v out ? 1.0 ? s disable time tdis from en > = 1.2 v to v out < 0.3 v rload = 5.0 (see figures 5 & 12) ? 1.0 5.0 s note: electrical parameters are guaranteed by correlation across the full range of temperature. 4. additional uvlo and ovlo thresholds ranging from uvlo and from ovlo can be manufactured. contact your on semiconductor representative for availability.
ncp391 http://onsemi.com 5 timing diagrams flag v out v in uvlo t on 0.3 v t start 1.2 v ncp391 http://onsemi.com 6 typical operating characteristics figure 7. startup v in = ch1, v out = ch3 figure 8. output turn off time v in = ch1, v out = ch2 figure 9. flag going up delay v out = ch3, flag = ch2 figure 10. alert delay v out = ch1, flag = ch3 figure 11. initial overvoltage delay v in = ch1, v out = ch2, flag = ch3 figure 12. disable time en = ch1, v out = ch2, flag = ch3 50 ms t on and t start version
ncp391 http://onsemi.com 7 typical operating characteristics figure 13. inrush current with c out = 100 f, i charge = 1 a, output wall adaptor inductance 1 h figure 14. output short circuit figure 15. output short circuit (zoom fig. 14)
ncp391 http://onsemi.com 8 voltage detection in out conditions v in > ovlo 0 < v in < uvlo and/or /en = 1 voltage detection in out conditions /en = 0 & uvlo < v in < ovlo figure 16. simplified diagram figure 17. simplified diagram operation the ncp391 provides overvoltage protection for positive voltage, up to 28 v. a low r ds(on) nmosfet protects the systems (i.e.: charger) connected on the vout pin, against positive overvoltage. at powerup, with en pin = low, the output is rising up t on soft ? start after the input overtaking undervoltage uvlo (figure 3). the ncp391 provides a flag output, which alerts the system that a fault has occurred. a t start additional delay, regarding available output (figure 3) is added between output signal rising up and to flag signal rising up. flag pin is an open drain output.
ncp391 http://onsemi.com 9 timer check check v in flag = low timer count timer check v in < uvlo or v in > ovlo check en check en v out = v in flag = high check v in v out = open flag = high check v in figure 18. state machine ovlo > v in > uvlo t < t on t = t on reset timer v out = 0 flag = low reset timer v in < uvlo or v in > ovlo v out = 0 flag = low timer count uvlo < v in < ovlo en = 0 en = 1 v in < uvlo or v in > ovlo uvlo < v in < ovlo en = 0 en = 1 t = t on v out = open v in < uvlo or v in > ovlo t < t on uvlo < v in < ovlo v out = v in
ncp391 http://onsemi.com 10 undervoltage lockout (uvlo) to ensure proper operation under any conditions, the device has a built ? in undervoltage lockout (uvlo) circuit. during v in positive going slope, the output remains disconnected from input until v in voltage is below uvlo, plus hysteresis, nominal. the flag output is tied to low as long as v in does not reach uvlo threshold. this circuit has a built ? in hysteresis to provide noise immunity to transient condition. additional uvlo thresholds ranging from uvlo can be manufactured. contact your on semiconductor representative for availability. overvoltage lockout (ovlo) to protect connected systems on v out pin from overvoltage, the device has a built ? in overvoltage lockout (ovlo) circuit. during overvoltage condition, the output remains disabled as long as the input voltage exceeds typical ovlo. additional ovlo thresholds ranging from ovlo can be manufactured. contact your on semiconductor representative for availability. flag output is tied to low until v in is higher than ovlo. this circuit has a built ? in hysteresis to provide noise immunity to transient conditions . flag output the ncp391 provides a flag output, which alerts external systems that a fault has occurred. this pin is tied to low as soon the ovlo threshold is exceeded or when the v in level is below the uvlo threshold. when v in level recovers normal condition, flag is held high, keeping in mind that an additional t start delay has been added between available output and flag = high. the pin is an open drain output, thus a pull up resistor (typically 1 m , minimum 10 k ) must be added to v bat . minimum v bat supply must be 2.5 v. the flag level will always reflects v in status, even if the device is turned off (en = 1). en input to enable normal operation, the en pin shall be forced to low or connected to ground. a high level on the pin, disconnects out pin from in pin. en does not overdrive an ovlo or uvlo fault. internal nmosfet the ncp391 includes an internal low r ds(on) nmos fet to protect the systems, connected on out pin, from positive overvoltage. regarding electrical characteristics, the r ds(on) , during normal operation, will create low losses on v out pin. as example: r load = 8.0 , v in = 5.0 v typical r ds(on) = 120 m i out = 615 ma v out = 8 x 0.615 = 4.926 v nmos losses = r ds(on) x iout 2 = 0.12 x 0.615 2 = 45 mw esd tests the ncp391 input pin fully supports the iec61000 ? 4 ? 2. 1.0 f (minimum) must be connected between v in and gnd, close to the device. that means, in air condition, v in has a 15 kv esd protected input. in contact condition, v in has 8.0 kv esd protected input. please refer to figure 19 to see the iec 61000 ? 4 ? 2 electrostatic discharge waveform. figure 19. electrostatic discharge waveform pcb recommendations the ncp391 integrates a 2 a rated nmosfet, and the pcb rules must be respected to properly evacuate the heat out of the silicon. figure 20. 60 80 100 120 140 160 180 200 0 100 200 300 400 500 600 700 copper heat spreader area (mm^2) theta ja (c/w) 0.25 0.5 0.75 1 1.25 1.5 1.75 max power ( w ) theta ja curve with pcb cu thk 1.0 oz theta ja curve with pcb cu thk 2.0 oz power curve with pcb cu thk 2.0 oz power curve with pcb cu thk 1.0 oz
ncp391 http://onsemi.com 11 ordering information device marking package shipping ? NCP391FCALT2G 391l wlcsp6 (pb ? free) 3000 / t ape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d. selection guide the ncp391 can be available in several undervoltage and overvoltage thresholds versions. part number is designated as follows: a ncp391fcxxt1g b code contents a uvlo typical threshold a: a = 2.95 v b ovlo typical threshold b: l = 7.4 v
ncp391 http://onsemi.com 12 package dimensions wlcsp6, 1.31x1.04 case 499bp ? 01 issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.50 millimeters a1 d 1.31 bsc e b 0.24 0.29 ed 0.40 bsc 0.56 d e a b pin a1 reference ed a 0.05 b c 0.03 c 0.05 c 6x b 32 a b 0.10 c a a1 a2 c 0.17 0.23 1.04 bsc 0.26 6x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 0.40 0.60 0.10 c 2x top view side view bottom view note 3 a2 recommended package outline ee 6x 1 ee 0.60 bsc 0.33 0.39 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp391/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative
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